Automation of IC layout with analog constraints

| A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibil-ity is detected as soon as possible, thus providing a robust and eecient design environment. In the proposed approach, performance speciications are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design ow. Examples drawn from industrial applications are reported to illustrate the eeectiveness of the approach.